The present invention relates generally to digital circuits, and more specifically, to a clock multiplexer circuit.
Integrated circuits are widely used in computer systems for performing various functions and include many electronic circuit modules that work in tandem. Examples of such electronic circuit modules include processors, logic gates, flip-flops, latches, system buses, and so forth. These circuits are often referred to as functional circuits. The functional circuits are driven by a clock. Depending on the system requirements, different functional circuits may require different clock signals (having different frequencies) for their operation; e.g., an integrated circuit may include one set of functional circuits that operates in a first clock domain and another set of functional circuits that operates in a second clock domain. Such integrated circuits are referred to as asynchronous integrated circuits.
A clock multiplexer is used to provide clock signals with different frequencies. FIG. 1A is a schematic block diagram of a clock multiplexer 100. The clock multiplexer 100 has two input terminals for receiving first and second input clock signals CLOK0 and CLK1, a select terminal for receiving a select signal SELECT and an output terminal for providing either of the first and second clock signals CLK0 and CLK1 as an output clock signal OUT CLOCK. FIG. 1B is a timing diagram of the CLK0, CLK1, SELECT and OUT CLOCK signals. The clock multiplexer 100 provides the first clock signal CLK0 as the output clock signal OUT CLOCK signal when the select signal SELECT is low and provides the second clock signal CLK1 as the output clock signal OUT CLOCK when the select signal SELECT is high. As shown in FIG. 1B, the select signal SELECT transitions from low to high when the first clock signal CLK0 is high and the second clock signal CLK1 is low, which introduces a glitch in the OUT CLOCK signal due to the first clock signal CLK0 being high and being provided at the output until the select signal SELECT goes high. Glitches in clock signals are undesirable as they lead to erroneous operation of the electronic circuit modules.
TO eliminate glitches, clock multiplexers are often designed using a combination of flip-flops and logic gates. One such conventional clock multiplexer 200 is illustrated in FIG. 2A. The clock multiplexer 200 includes four flip-flops (first through fourth) 202a-202d, four AND gates (first through fourth) 204a-204d, a NOT gate 206 and an OR gate 208. The first and second flip-flops 202a, 202b are connected in series and clocked with a first clock signal CLK0. Similarly, the third and fourth flip-flops 202c, 202d are connected in series and clocked with a second clock signal CLK1. The output of the second flip-flop 202b and the first clock signal CLK0 are input to the second AND gate 204b, and the output of the fourth flip-flop 202d and the second clock signal CLK1 are input to the fourth AND gate 204d. The outputs of the second and fourth AND gates 204b, 204d are input to the OR gate 208 and the output of the OR gate 208 is the clock out signal.
The input to the first flip-flop 202a is an output of the first AND gate 204a, and the inputs to the first AND gate 204a are an inverted select signal SELECT (output by the NOT gate 206) and the inverted output of the fourth flip-flop 204d. Similarly, the input to the third flip-flop 202c is an output of the third AND gate 204c, and the inputs to the third AND gate 204c are the select signal SELECT and the inverted output of the second flip-flop 202b. 
Referring now to FIG. 2B, which is a timing diagram of the signals of the multiplexer 200, the operation of the clock multiplexer 200 will be explained. Assuming the select signal SELECT to be low and the output the second flip-flop 202b to be high, the high output of the second flip-flop 202b causes the output of the to reflect the state of the first clock signal CLK0. The OR gate 208 thus receives and outputs the first clock signal CLK0 as the output clock signal OUT CLOCK (as long as the other input to the OR gate 208 is low). The inverting output terminal of the second flip-flop 202b is low, which (along with the low select signal SELECT) causes the third AND gate 204c to output a low signal (CLK1 SEL), which causes the third flip-flop 202c to output a low signal (CLK1 EN) at a positive edge of the second clock signal CLK1, which in turn causes the fourth flip-flop 202d to output a low signal at a subsequent negative edge of the second clock signal CLK1. Since the output of the fourth flip-flop 202d is low, the output of the fourth AND gate 204d is low. The inverting output terminal of the fourth flip-flop 202d is high, so a high signal is input to the first AND gate 204a. The first AND gate 204a also receives the inverted SELECT signal, which also is high, and so the first AND gate outputs a high signal (CLK0 SEL).
When the select signal SELECT goes from low to high, the first AND gate 204a receives a low select signal SELECT by way of the NOT gate 206, which causes the output of the first AND gate 204a to go low (CLK0 SEL), which causes the output of the first flip-flop 202a to go low (CLK0 EN) at a positive edge of the first clock signal CLK0, which in turn causes the output of the second flip-flop 202b to go low signal at a subsequent negative edge of the first clock signal CLK0. The low output of the second flip-flop 202b disables the second AND gate 204b, which gates the CLK0 signal. The inverted output of the second flip-flop 202b is high, and is input to the third AND gate 204c. The third AND gate 204c also receives the SELECT signal, which is high, and so the output of the third AND gate 204c goes high (CLK1 SEL), which the output of the third flip-flop 202c to go high (CLK1 EN) at a positive edge of the second clock signal CLK1, which in turn causes the output of the fourth flip-flop 202d to go high at a subsequent negative edge of the second clock signal CLK1, which enables the fourth AND gate 204d to output the second clock signal CLK1 (CLK1 OUT). The OR gate 208 thus receives and provides the second clock signal CLK1 as the output clock signal OUT CLOCK.
As can be seen in FIG. 2B, the OR gate 208 outputs two extra clock cycles of the first clock signal CLK0 when the select signal SELECT transitions from low to high. Further when the first clock signal CLK0 is gated during switching, the CLK1 EN signal goes high at the next positive edge of the second clock signal CLK1 (second clock cycle of CLK1 as seen in FIG. 2). The CLK1 OUT signal is generated at the end of the second clock cycle of the second clock signal CLK1. In other words, when the select signal SELECT transitions from low to high, two additional clock cycles of the first clock signal CLK0 are output and two clock cycles of the second clock signal CLK1 are wasted before the second clock signal CLK1 is output. This negatively impacts the performance of the electronic circuit modules. Moreover, if either of the first and second clock signals CLK0 and CLK1 stops during transition, the conventional clock multiplexer 200 will stop operating.
Therefore, it would be advantageous to have a clock multiplexer that efficiently switches between the input clock signals, and that overcomes the above-mentioned limitations of conventional clock multiplexers.